Add a Controller to the ALU VHDL Code: The Controller is responsible for generat
ID: 1730368 • Letter: A
Question
Add a Controller to the ALU VHDL Code:
The Controller is responsible for generating the required control signals for all functional blocks in your design. Select is used to select the functional unit for the corresponding operation in Arithmetic Unit. Sel1 and Sel2 are utilized as select signals of MUXes. Sel_Cout is used to control the cout of ALU, its value is “1” when ALU doing arithmetical operations; otherwise, it is “0”. Direction bit determines the direction of shift operation and Type bit determines the way of shifting. Opcode is used to select the type of operation and could be used as input to all three functional units.
--VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU16bit is
Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Mode : in STD_LOGIC;--c
OpCode : in STD_LOGIC_VECTOR(2 downto 0);--s
ALUout : out STD_LOGIC_VECTOR(15 downto 0);--result
Cou : out STD_LOGIC);
end ALU16bit;
architecture Behavioral of ALU16bit is
component Arithmetic is
port ( A: in STD_LOGIC_VECTOR(15 downto 0);
B:in STD_LOGIC_VECTOR(15 downto 0);
OpCode:in STD_LOGIC_VECTOR(1 downto 0);
ArithOut: in STD_LOGIC_VECTOR(15 downto 0);
Cout: out STD_LOGIC);
end component;
component Logic is
Port (A : in STD_LOGIC_VECTOR (15 downto 0);
B: in STD_LOGIC_VECTOR (15 downto 0);
Opcode: in STD_LOGIC_VECTOR (2 downto 0);
LogicOut: out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Shift is
Port (A: in STD_LOGIC_VECTOR (15 downto 0);
c: in STD_LOGIC;
s: in STD_LOGIC;
Shiftout : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component MUX is
Port ( a,b,c,d:in STD_LOGIC_VECTOR(15 downto 0);
s: in STD_LOGIC_VECTOR(1 downto 0);
y: out STD_LOGIC_VECTOR(15 downto 0));
end component;
signal sg_arith :STD_LOGIC_VECTOR(15 downto 0);
signal sg_logic :STD_LOGIC_VECTOR(15 downto 0);
signal sg_shift :STD_LOGIC_VECTOR(15 downto 0);
begin
p0: Arithmetic port map(A,B,OpCode, sg_arith);
p1: Logic port map(A,B,Opcode, sg_logic);
p2: Shift port map(A,Mode,Opcode(1),sg_shift);
p3: MUX port map(sg_arith, sg_logic, sg_shift,"ZZZZZZZZZZZZZZZZ", Opcode(3 downto 2), ALUout);
end Behavioral;
The following table summarizes the overall behavior of the ALU: Operation A nor B A nand A or B A and B A xor B A xnor B Not A Not B Opcode Mode 0 0 0 0 0 0 0 0 001 010 011 100 101 110 001 010 011 100 101 110 A B A -B Increment A (A +1) Shift Left(A,B) Shift Right(A,B) Rotate Left(A,B) Rotate Right(A,B)Explanation / Answer
FPGA Controller can be added to the ALU VHDL Code.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU16bit is
Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Mode : in STD_LOGIC;--c
OpCode : in STD_LOGIC_VECTOR(2 downto 0);--s
ALUout : out STD_LOGIC_VECTOR(15 downto 0);--result
Cou : out STD_LOGIC);
end ALU16bit;
architecture Behavioral of ALU16bit is
component Arithmetic is
port ( A: in STD_LOGIC_VECTOR(15 downto 0);
B:in STD_LOGIC_VECTOR(15 downto 0);
OpCode:in STD_LOGIC_VECTOR(1 downto 0);
ArithOut: in STD_LOGIC_VECTOR(15 downto 0);
Cout: out STD_LOGIC);
end component;
component Logic is
Port (A : in STD_LOGIC_VECTOR (15 downto 0);
B: in STD_LOGIC_VECTOR (15 downto 0);
Opcode: in STD_LOGIC_VECTOR (2 downto 0);
LogicOut: out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Shift is
Port (A: in STD_LOGIC_VECTOR (15 downto 0);
c: in STD_LOGIC;
s: in STD_LOGIC;
Shiftout : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component MUX is
Port ( a,b,c,d:in STD_LOGIC_VECTOR(15 downto 0);
s: in STD_LOGIC_VECTOR(1 downto 0);
y: out STD_LOGIC_VECTOR(15 downto 0));
end component;
signal sg_arith :STD_LOGIC_VECTOR(15 downto 0);
signal sg_logic :STD_LOGIC_VECTOR(15 downto 0);
signal sg_shift :STD_LOGIC_VECTOR(15 downto 0);
begin
p0: Arithmetic port map(A,B,OpCode, sg_arith);
p1: Logic port map(A,B,Opcode, sg_logic);
p2: Shift port map(A,Mode,Opcode(1),sg_shift);
p3: MUX port map(sg_arith, sg_logic, sg_shift,"ZZZZZZZZZZZZZZZZ", Opcode(3 downto 2), ALUout);
end Behavioral;
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