1. Verilog Implementation Write the VERILOG code to implement the following Fini
ID: 1716784 • Letter: 1
Question
1. Verilog Implementation Write the VERILOG code to implement the following Finite State Machine. This FSM has four states: St0, St1, St2, and St3. There are three inputs: Reset, A and B. There is only one output: Q1. A value of x for either of the inputs indicates that it is a "don't care" for that transition In addition to writing the Verilog code, please also answer the following questions: What is the minimum number of flip-flops needed to implement this FSM? Is this a Mealy or a Moore Machine? 1. 2.Explanation / Answer
Module StateMachine
input A; //Input of the system
input B; //Input of the system
input Clk;//Input of the system
input Reset;//Input of the system
output Q1; //The only output of the system
Localparam st0=0, st1=1, st2=2, st3=3; //Definition of the states
reg [1:0] Actual_State;
reg [1:0] Next_State;
always @*
begin
case (Actual_State)
st0: begin
if (A==0)
Next_State=st2;
else if (A==1)
Next_State=st1;
end
st1: begin
if (A==1)
Next_State=st3
end
st2: begin
if (A==1 and B==0)
Next_State=st1
if (A==1 and B==!)
Next_State=st3
end
st3:begin
if (A==0 and B==1)
Next_State=st2
if (A==0 and B==0)
Next_State=st0
default: Next_State=st0
endcase
end
always @ (posedge Clk or negedge)
begin
if (!Reset)
Actual_State<=0;
else
Actual_State<-Next_State
end
always @*
begin
if (Actual_State=st0 or Actual_State=st1)
Q1=1
else
Q1=0
1)
The minimum number of Flip Flops to implemente this circuit
is two, because with four states you will need two boolean
state variables:
00 State 0
01 State 1
11 State 2
10 State 3
2) The system is moore.
In moore systems outputs only depends on actual state
In mealy systems outputs depends on actual state and inputs
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