this is my 3 bit up counter or 3-8 decoder in quartus that has enable, read and

Question

this is my 3 bit up counter or 3-8 decoder in quartus that has enable, read and a clk.the problem is it shows error that instant 15 cant be used. can someone please help me with the correction.

or if the rtl file can be generated please coz when i tried it says nativelink error.this is the

library ieee;
use ieee.std_logic_1164.all;

ENTITY tr IS
port (a: in std_logic_vector(2 downto 0);
e: in std_logic ;
clk:in std_logic;
read: in std_logic;
rst: in std_logic;
y: out std_logic_vector(7 downto 0)
);
END tr;

--
ARCHITECTURE RTL OF tr IS
BEGIN
process (e , a)
begin
if e = '1' then
if a = "000" then y <="00000001";
elsif a = "001" then y <="00000010";
elsif a = "010" then y <="00000100";
elsif a = "011" then y <="00001000";
elsif a = "100" then y <="00010000";
elsif a = "101" then y <="00100000";
elsif a = "110" then y <="01000000";
elsif a = "111" then y <="10000000";
else null;
end if;
end if;
end process;
END ARCHITECTURE RTL;

Explanation / Answer

Try the below code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder3x8 is
Port ( i : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder3x8;
architecture Behavioral of decoder3x8 is
begin
process(i)
begin
case i is
when "111" => y<="00000001";
when "110" => y<="00000010";
when "101" => y<="00000100";
when "100" => y<="00001000";
when "011" => y<="00010000";
when "010" => y<="00100000";
when "001" => y<="01000000";
when "000" => y<="10000000";
when others => null;
end case;
end process;
end Behavioral;

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