The following circuit is a 4-bit parallel/serial load shift register with enable

Question

The following circuit is a 4-bit parallel/serial load shift register with enable input. Shifting operation: s_1=0. Parallel load: s_1=1. Note that Q = Q_3 Q_2 Q_1 Q_0. D = D_3 D_2 D_1 D_0 Write a structural VHDL code. You MUST create a file for: i) flip flop, ii) MUX 2-to-l, and iii) top file (where you will interconnect the flip flops and MUXes). Provide a printout. Write a VHDL test bench according to the timing diagram shown below. Complete the timing diagram by simulating your circuit (Timing Simulation). The clock frequency must be 50 MHz with 50percentage duty cycle. Provide a printout.

Explanation / Answer

vhdl code for D flip flop

library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff_srss is
port (
d,clk,reset,set : in STD_LOGIC;
q : out STD_LOGIC);
end d_ff_srss;

architecture d_ff_srss of d_ff_srss is
begin
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
q <= '0';
elsif set='1' then
q <= '1';
else
q <= d;
end if;
end if;
end process;
end d_ff_srss;

The 2 to 1 Line Multiplexer VHDL Program

Test Bench

Top files

4 bit parallel/serial load shift register

-- entity
entity SHIFT4 is
port (JP, KN, MRN, PEN, CLK : in std_logic; -- asynchronous reset overrides all
D : in std_logic_vector(3 downto 0);
Q3N : out std_logic;
Q : inout std_logic_vector(3 downto 0));
end entity SHIFT4;

-- architecture
architecture BEHAV of SHIFT4 is
begin
STATE_CHANGE : process (CLK, MRN) is
begin
if (MRN = '0') then
Q(3 downto 0) <= "0000";
Q3N <= '1';
elsif CLK'event and CLK = '1' then
if (PEN = '0') then
Q(3 downto 0) <= D(3 downto 0);
Q3N <= not(D(3));
else
Q(0) <= (not(Q(0)) and JP) or (Q(0) and KN);
Q(1) <= Q(0);
Q(2) <= Q(1);
Q(3) <= Q(2);
Q3N <= not(Q(2));
end if;
end if;
end process STATE_CHANGE;
end architecture BEHAV;

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