A \"ring counter\" is a group of master-slave D flip-flop connected in sequence
ID: 1716047 • Letter: A
Question
A "ring counter" is a group of master-slave D flip-flop connected in sequence out put-to-input, to make a circular shift register. One or more of the D FF's is set to one and the rest are set to 0. Since the flip-flops are connected in a "ring." the pattern of bits continually rotates around the shift register. If one stage of the shift register is arbitrarily selected as the "output," this stage will output O's and 1's in the sequence that the I and 0 values pass that particular output. If only one I is set into the register, then a I passes the chosen output only 1 clock pulse in every pulses, N being the number of DFF's in the ring. The ring counter in this case creates a new clock, with a frequency of 1/N compared to the regular clock. More complex ring counters can be constructed, however, such as the one below. In the case shown, two D FF's are set to 1 (#'s 2 and 5). and the rest to 0 by the "Reset" pulse. However, the outputs of FF's 2 and 4 are OR'ed together to produce a very complex output sequence. After the Reset pulse shown on the timing diagram, the clock starts and runs continually. Show the output "f" for the number of clock cycles indicated below.Explanation / Answer
One way to eliminate the undesirable condition of the indeterminate state in the RS flip flop is to ensure that inputs S and R are 122 never equal to 1 at the same time.The D flip flop is a modification of the clocked SR flip-flop. It has only two inputs: D and CP. The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state.
The binary information present at the data input of the D flip flop is transferred to the Q output when the CP input is enabled. The output follows the data input as long as the pulse remains in its 1 state. When the pulse goes to 0, the binary information that was present at the data input at the time the pulse transition occurred is retained at the Q output until the pulse input is enabled again.
The The characteristics table of the D flip flop shows that the next state of the D flip flop is independent of the present state since Q (t+1) is equal to the input D whether Q is equal to 0 or 1. This means that an input pulse will transfer the value of input D into the output of the flip flop independent of the value of the output before the pulse was applied. The characteristics equation shows clearly that Q (t+1) = D.
Next the D flip flop is designed with the help of the characteristic equation. The flip flop is designed by two ways. First method is using majority gates and the second method is using a QCA binary wire. In the first method the flip flop is constructed by using 3 majority gates and 1 inverter as shown in Figure.
The circuit have one input D and along with one control input Clock. The output Q of the flip flop is fed back to the majority gate M3 and combined with the input D to produce the output Q. Here the gate M1 act as an AND gate and M2 act as an OR gate. The gate M3 is designed to perform OR operation which combine the output of Majority gate M1 and M2.Hence the output of the gate M3 produce the desired characteristic Equation .
The QCA implementation of the D flip flop is shown in Figure 6.9. The QCA implementation requires 69 cells, with an area of 93,686 nm2 and this also required less number of cells than previous implementations. This is achieved by using cell minimization techniques.
D flip flop Latching is effectively accomplished through timing by using a four-phase clocking arrangement. Therefore, a D-type FF can be constructed by a QCA binary wire with four clocking zones as shown in Figure. In this case, the input signal is delivered to the output after at least one complete clock cycle delay and control is accomplished by timing.
The relative simplicity of a D-FF seems to suggest that sequential design in QCA could be achieved at ease within the Cartesian layout and have been proposed by 125 Huang et al (2007). However, timing and signal delay must be carefully considered. Figure 6.10 Layout of D flip flop using binary wire The wire which is clocked from left to right with increasing clocking zones will carry information in the same direction. The clock signals act to pump information in the circuit as a result of the successive latching and unlatching in cells connected to different clock phases. Figure shows a wire connected to different clock zones. Each group of cells connected to a particular clocking zone. The clocked QCA wire is used to carry the information which is constructed by regular QCA cells. Hence in the QCA wire input and outputs are equal and it act as a D flips flop. The D flip flop is implemented by only 16 cells.
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