True and False questions : 1- A timing diagram shows X\'s for a short period of

Question

True and False questions :

1- A timing diagram shows X's for a short period of time. Those X's indicate the signal is an invalid state.

2- Failure to meet a setup time can cause metastability.

3- S= 0 and R=0 produces an invalid output on a latch constructed with NAND gates.

4- A FSM has 8 states. After using an implication table the FSM is reduced to 7 states. since the original FSM both require 3 registers, there is no advantage in implementing the reduced FSM ( please if you can explain this one, )

5- Two states in FSM have different output. They therefore connot be equivalent.

6- In Moore FSM the outputs depend on the current state and current input

7-All FSMs must have defined initial state

8- A synchronous input always reqiures a clock

9- In a Mealy FSM the present state and the next state (regardless of the input ) must be different.

Explanation / Answer

True True True True, because still 3 registers are required to implement the reduced implication table. True False, in Moore machine output depends only on current state. True True False

Related Questions

Navigate

• Browse (All)
• Browse T
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.