True and False questions: 1- It is good design partctice to register the output

Question

True and False questions:

1- It is good design partctice to register the output of Mealy FSMs

2- A full- encoded FSM with 2,122 states will require more than 20 registers to implement

3- A PAL16R8 can implement ant one-hot encoded with 8 or fwer states

4- The setup time for a 74LVC2G74 register operating at 3.3 Vcc is at least 1.3 ns

5-The Q-bar output of a 74LVC2G74 is connected to the D input. Vcc is 5 V. this device can be clocked at 200 MHz

6- Any circuit that is built with registers could also have been built using latches

7- If the PRESET input on a 74LVC2G74 is arrested for at least 2 ns, the Q output will be equal logic 1 ( assume Vcc=5 V )

8- A latch is constructed with two NAND gates. Suppose an input is applied that causes the outputs to change. The Q and Q-bar output will have the same propagation delay.

9- A positive-edge triggered device responds when the clock changes from logic 1 to logic 0

Explanation / Answer

It is good design partctice to register the output of Mealy FSMs (TRUE)

A Mealy FSM is a state machine where one or more of the outputs is a function of the present state and one or more of the inputs.

Moore FSM is a state machine where the outputs are only a function of the present state.

2. A full- encoded FSM with 2,122 states will require more than 20 registers to implement. (FALSE)

3. A PAL16R8 can implement ant one-hot encoded with 8 or fewer states (TRUE)

            Advantages

Determining the state has a low and constant cost of accessing one flip-flop

Changing the state has the constant cost of accessing two flip-flops

Easy to design and modify

Easy to detect illegal states

Takes advantage of an FPGA's abundant flip-flops

            Using a one-hot implementation typically allows a state machine to run at a faster clock     rate than any other encoding of that state machine

            Disadvantages

Requires more flip-flops than other encodings, making it impractical for PAL devices

Many of the states are illegal

4.   The setup time for a 74LVC2G74 register operating at 3.3 Vcc is at least 1.3 ns(FALSE)

At least 1.0 ns (see data sheet)                                        

5... The Q-bar output of a 74LVC2G74 is connected to the D input. Vcc is 5 V. this device can be clocked at 200 MHz(FALSE)

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

6.    Any circuit that is built with registers could also have been built using latches(FALSE)

            Built using Flip-flops

7.    If the PRESET input on a 74LVC2G74 is arrested for at least 2 ns, the Q output will be equal logic 1 ( assume Vcc=5 V ) (FALSE)

8.    A latch is constructed with two NAND gates. Suppose an input is applied that causes the outputs to change. The Q and Q-bar output will have the same propagation delay. (FALSE)

flip-flop takes to change its output after the clock. Occurs Different propagation delays

9.   A positive-edge triggered device responds when the clock changes from logic 1 to logic 0. (FALSE)

            positive-edge triggered devices are 0 to 1 and negitive-edge triggered devices are 1 to 0

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