Logic Circuits 101: KEEP IT SIMPLE No need for the actual circuit design, just t

Question

Logic Circuits 101:
KEEP IT SIMPLE

No need for the actual circuit design, just the VHDL file will suffice.
Develop a VHDL file necessary to meet the following requirements:

In a certain chemical-processing plant, a liquid chemical is used in a manufacturing process. The chemical is stored in three different tanks. A level sensor in each tanks produces a HIGH voltage when the level of chemical in the tank drops below a specified point.

Write a VHDL file that monitors the chemical level in each tank and indicates when the level in any two of the tanks drops below the specified point.

Please type the code and paste the screenshot, comparing handwritten codes to a typed one is extremely difficult sometimes. Thank-you!

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Monitor_sys is
Port ( tank1,tank2,tank3 : in STD_LOGIC;
indicator : out STD_LOGIC);
end Monitor_sys;

architecture Behavioral of Monitor_sys is

begin
indicator<=(tank1 and tank2) or (tank2 and tank3) or (tank1 and tank3);

end Behavioral;

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