This question is for 130nm process. Problem 4 A two stage operational amplifier

Question

This question is for 130nm process.

Problem 4 A two stage operational amplifier has been designed according to figure 9.25 in the textbook. The 130nm CMOS process has been used, and the length of all transistor is equal to 0.4kum. The component parameters: VDD 1.2V, I 200HA, W2 20um, 2pF Re-design the amplifier using an NMos input pair instead of a PMos. The bias current levels should be same and also the transconductance of corresponding transistors. T compensation and load capacitors should not be The magnitude of RIAs will not change, but you changed. may change polarity Draw the schematic. (2p) Calculate the transistor dimensions. Also calculate Rz so that the transfer function zero is located at infinite frequency. Calculate the unity gain bandwidth, the phase margin, and the slew rate. (4p) Use long-channel equations To simplify calculations all capacitances except Cgs, CL and C can be neglected

Explanation / Answer

there is no fig 9.25 in the question. kindly attach the figure so the problem could be solved.

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