17. According to its design specification, the timer circuit delaying the closin
ID: 1707135 • Letter: 1
Question
17. According to its design specification, the timer circuit
delaying the closing of an elevator door is to have a capacitance
of 32.0 F between two points A and B. When one
circuit is being constructed, the inexpensive but durable
capacitor installed between these two points is found to
have capacitance 34.8 F. To meet the specification, one
additional capacitor can be placed between the two points.
Should it be in series or in parallel with the 34.8-F
capacitor? What should be its capacitance? What If?
The next circuit comes down the assembly line with capacitance
29.8 F between A and B. To meet the specification,
what additional capacitor should be installed in series or in
parallel in that circuit?
Explanation / Answer
Capacitors in series add like this:
1/Cs = 1/C + 1/C ....
while capacitors in parallel add up like this:
Cp = C + C... etc.
So added caps in series lowers the the capacitance. For (a) then it is series and we need a capacitor that is 256.4uF so that the total capacitance is 32uF .
For (b) we need a 0.5uF capacitor to make the 30uF.
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