[Problem 2-9 Pts] Part a) Write a Verilog module that uses the DE10-Lite\'s 50MH

Question

[Problem 2-9 Pts] Part a) Write a Verilog module that uses the DE10-Lite's 50MHz or 10MHz clock signal (MAX10_CLK1_50 or ADC_CLK_10) and divides it down to 1 hz and 0.5Hz. Connect the 1Hz and 0.5Hz outputs to LEDs on the display. Part b) Create a second Verilog counter that counts from 0 to 9 using the 1Hz clock signal you created in part 1. Using the 7 segment display code from either project 1 or from my example code, display the output of the counter on HEXO display. Part c) Record a short video segment of the DE10-lite board that shows the LEDs blinking and 7 segment display counting.

Explanation / Answer

The following program code divides input clock frequency of 50Mhz to 1hz.

Algorithm followed: Frequency divider works on the basic principle of holding the master clock for few cycles to generate new clock with new frequency. Suppose if at positive edge of input or master clock, i turn on a counter and put the output at certain pin(new clock to be generated) as logic high. By the time counter reaches to zero, many clock cycles of input clock are passed. But our new clock is at logic high by this time you must not forget this. Thus we get first half cycle of our new clock viz 1 Hz. Same process repeated for negative half cycle. Counter values chosen accordingly as per the desired frequency Divisor.

REGISTER MODULE

module RegX(I, Q, clk, reset);
input clk, reset;
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;

wire clk_1Hz;
NewClock clock_generator(clk, reset, clk_1Hz);

always@(posedge clk_1Hz) begin     
    if (reset == 1)
        Q <= 4'b0000;  
    else
        Q <= I;

end
endmodule

MAIN MODULE

module NewClock(clk, reset, clk_1Hz);
input clk, reset;
output clk_1Hz;

reg clk_1Hz = 1'b0;
reg [27:0] counter;

always@(posedge reset or posedge clk)
begin
    if (reset == 1'b1)
        begin
            clk_1Hz <= 0;
            counter <= 0;
        end
    else
        begin
            counter <= counter + 1;
            if ( counter == 25_000_000)
                begin
                    counter <= 0;
                    clk_1Hz <= ~clk_1Hz;
                end
        end
end
endmodule

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