a) In any chemical fabrication process (eg. wet etching or CVD) there are two ma
ID: 1009785 • Letter: A
Question
a) In any chemical fabrication process (eg. wet etching or CVD) there are two main regions
where the reaction rate is dominated by different processes. Name them and explain what each of
those regions mean. Also change in what processing condition causes a significant change in the
deposition or etching process? Sketch a typical curve showing how the process rate is changed
by the alteration of that condition. Predict the effect of doubling the reactant concentration NG in
a CVD system for both regions. Predict the effect of doubling the gas flow velocity in a CVD
system in both regions?
b) Give two examples for the use of CVD technology in CMOS device manufacturing processes.
Indicate their significance and preferred CVD technology tools (PECVD, LPCVD etc.) for these
steps. Briefly explain why are these tools are preferred?
Explanation / Answer
A handful of companies produce most of the silicon wafers (Fig. 1–3b) used in the world. Hundreds of silicon device fabrication lines purchase these wafers as their starting material. A large wafer fab can process 40,000 silicon wafers into circuits each month. The simple example of the device fabrication process shown in Fig. 3–1 includes (a) formation of an SiO2 layer, (b) its selective removal, (c) introduction of dopant atoms into the wafer surface, and (d) dopant diffusion into silicon. VLSI! ULSI! GSI! The complexity or density of integration of ICs is sometimes described by the names LSI (large-scale integration, 104 transistors on a chip), VLSI (very large-scale integration, 106 transistors on a chip), ULSI (ultra-large-scale integration), and GSI (giga-scale integration). In actuality, all these terms are used to describe circuits and technologies of wide ranges of size and complexity and simply mean “large IC.” FIGURE 3–1 Some basic steps in the silicon device fabrication process: (a) oxidation of silicon; (b) selective oxide removal; (c) introduction of dopant atoms; and (d) diffusion of dopant atoms into silicon. Si SiO2 SiO2 selectively etched Si Dopant atoms introduced into exposed silicon Dopant atoms diffuse into Si SiO2 Si SiO2 Si SiO2 (a) (b) (c) (d) Hu_ch03v3.fm Page 60 Thursday, February 12, 2009 12:28 PM 3.2 Oxidation of Silicon 61 Combination of these and other fabrication steps can produce complex devices and circuits. This step-by-step and layer-upon-layer method of making circuits on a wafer substrate is called planar technology. A major advantage of the planar process is that each fabrication step is applied to the entire silicon wafer. Therefore, it is possible to not only make and interconnect many devices with high precision to build a complex IC, but also fabricate many IC chips on one wafer at the same time. A large IC, for example, a central processor unit or CPU, may be 1–2 cm on a side, and a wafer (perhaps 30 cm in diameter) can produce hundreds of these chips. There is a clear economic advantage to reduce the area of each IC, i.e., to reduce the size of devices and metal interconnects because the result is more chip per wafer and lower cost per chip. Since 1960, the world has made a huge investment in the planar microfabrication technology. Variations of this technology are also used to manufacture flat-panel displays, micro-electro-mechanical systems (MEMS), and even DNA chips for DNA screening. The rest of this chapter provides an introduction to the modern device processing technology. Perhaps the most remarkable advances have occurred in the fields of lithography (Section 3.3) and interconnect technology (Section 3.8). These are also the two areas that soak up the largest parts of the IC fabrication cost.
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